The SAFEPROCESS TC promotes on-line fault and cyber-attack detection, isolation, estimation, and diagnosis, with a view to predictive maintenance and supervision, as well as fault tolerant and cyber-secure control. It addresses residual generation, residual evaluation, performance monitoring, statistical hypothesis testing, on-line change detection, software sensors, active input signal generation for FDI, decision making, controller reconfiguration and switching, accommodation against cyber-attacks. It relies on system theory, statistics, system identification, statistical process control, artificial intelligence and optimization theory. Processes described by models qualified as linear/ non-linear, uncertain, hybrid, lumped/ distributed parameters, rule-based and discrete-event models are considered. This TC also promotes analysis tools such as failure mode and effects analysis, severity analysis and reliability theory to achieve fault tolerant designs.
Scope of TC6.4
The SAFEPROCESS TC promotes on-line fault and cyber-attack detection, isolation, estimation, and diagnosis, with a view to predictive maintenance and supervision, as well as fault tolerant and cyber-secure control.
Related from TC6.4 Fault Detection, Supervision & Safety (SAFEPROCESS)
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CAMS 2027
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SIMS 2026
The 67th International Conference of Scandinavian Simulation Society, SIMS 2026
Welcome Message from the TC6.4 Chair 2023–2026
The IFAC Technical Committee on Fault Detection, Supervision and Safety of Technical Processes (SAFEPROCESS) focuses on control system safety, including fault diagnosis, reliability analysis, fault-tolerant control, and predictive maintenance.